CPU Cycle count relating to crystal clock count question

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funnyguy
Snes9x White Belt
Posts: 4
Joined: Sun May 01, 2016 12:16 pm

CPU Cycle count relating to crystal clock count question

Post by funnyguy » Mon Jul 17, 2017 5:32 am

I am checking to have a better understanding of the clock cycle of each instructions.

I have encountered some problem and hope someone could explain.

I use the debug version of Snes9x to log a game ( Falcom : popful mail )

These are the first twelve instructions after a reset

Code: Select all

$00/8001 18       CLC                     A:0000 X:0000 Y:0000 D:0000 DB:00 S:01FF P:EnvMXdIzC HC:0198 VC:000 FC:00 I:00
$00/8002 FB          XCE                     A:0000 X:0000 Y:0000 D:0000 DB:00 S:01FF P:EnvMXdIzc HC:0220 VC:000 FC:00 I:00
$00/8003 E2 14       SEP #$14                A:0000 X:0000 Y:0000 D:0000 DB:00 S:01FF P:envMXdIzC HC:0242 VC:000 FC:00 I:00
$00/8005 C2 28       REP #$28                A:0000 X:0000 Y:0000 D:0000 DB:00 S:01FF P:envMXdIzC HC:0272 VC:000 FC:00 I:00
$00/8007 A9 FE 01    LDA #$01FE              A:0000 X:0000 Y:0000 D:0000 DB:00 S:01FF P:envmXdIzC HC:0302 VC:000 FC:00 I:00
$00/800A 1B          TCS                     A:01FE X:0000 Y:0000 D:0000 DB:00 S:01FF P:envmXdIzC HC:0334 VC:000 FC:00 I:00
$00/800B 4B          PHK                     A:01FE X:0000 Y:0000 D:0000 DB:00 S:01FE P:envmXdIzC HC:0356 VC:000 FC:00 I:00
$00/800C AB          PLB                     A:01FE X:0000 Y:0000 D:0000 DB:00 S:01FD P:envmXdIzC HC:0386 VC:000 FC:00 I:00
$00/800D A0 00       LDY #$00                A:01FE X:0000 Y:0000 D:0000 DB:00 S:01FE P:envmXdIZC HC:0422 VC:000 FC:00 I:00
$00/800F A2 01       LDX #$01                A:01FE X:0000 Y:0000 D:0000 DB:00 S:01FE P:envmXdIZC HC:0446 VC:000 FC:00 I:00
$00/8011 A9 00 42    LDA #$4200              A:01FE X:0001 Y:0000 D:0000 DB:00 S:01FE P:envmXdIzC HC:0470 VC:000 FC:00 I:00
$00/8014 5B          TCD                     A:4200 X:0001 Y:0000 D:0000 DB:00 S:01FE P:envmXdIzC HC:0502 VC:000 FC:00 I:00
It is known that HC is count of the 21.477MHz clock, from the documents, each CPU cycle can have 6 or 8 or 12 counts of the 21.477MHz clock

the first two instruction CLC, XCE each used ( 220-198 ) (242-220) = 22 clocks
referring to the 65816 documents, this two instruction takes 2 machine cycles

As the ROM is $00/8000 range, reading this ROM opcode used 8 ( 21MHz clock) clocks, however the execution cycle will be 22-8 = 14 ( this is not 6/8/12 as mentioned in the documents, why is this so ? )

Furthermore, referring to the $00/800D 3 instructions LDY, LDX, LDA each takes 3, 3, 4 cycles ( index is 8 bit, M is 16 bit, so ACC fetches 2 bytes )
referring to HC they are ( 446-422 ), ( 470-446), ( 502-470 ) = 24, 24, 32 clock count.
This is correct for 3, 3, 4 CPU cycles each taking 8 clocks.

Can anyone tell me how the actual clock counts work ?

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OV2
Official Win32 Porter/Dev
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Joined: Thu Aug 30, 2007 10:15 pm

Re: CPU Cycle count relating to crystal clock count questio

Post by OV2 » Sun Jul 23, 2017 9:58 pm

The version you are using might simply not be that accurate. In the current build it looks like this:

Code: Select all

$00:8001 18          CLC                     A:0032 X:0000 Y:000E D:0000 DB:00 S:01F6 P:EnvMXdIZC HC:0198 VC:000 FC:00 000
$00:8002 FB          XCE                     A:0032 X:0000 Y:000E D:0000 DB:00 S:01F6 P:EnvMXdIZc HC:0212 VC:000 FC:00 000
$00:8003 E2 14       SEP #$14                A:0032 X:0000 Y:000E D:0000 DB:00 S:01F6 P:envMXdIZC HC:0226 VC:000 FC:00 000
$00:8005 C2 28       REP #$28                A:0032 X:0000 Y:000E D:0000 DB:00 S:01F6 P:envMXdIZC HC:0248 VC:000 FC:00 000
$00:8007 A9 FE 01    LDA #$01FE              A:0032 X:0000 Y:000E D:0000 DB:00 S:01F6 P:envmXdIZC HC:0270 VC:000 FC:00 000
$00:800A 1B          TCS                     A:01FE X:0000 Y:000E D:0000 DB:00 S:01F6 P:envmXdIzC HC:0294 VC:000 FC:00 000
$00:800B 4B          PHK                     A:01FE X:0000 Y:000E D:0000 DB:00 S:01FE P:envmXdIzC HC:0308 VC:000 FC:00 000
$00:800C AB          PLB                     A:01FE X:0000 Y:000E D:0000 DB:00 S:01FD P:envmXdIzC HC:0330 VC:000 FC:00 000
$00:800D A0 00       LDY #$00                A:01FE X:0000 Y:000E D:0000 DB:00 S:01FE P:envmXdIZC HC:0358 VC:000 FC:00 000
$00:800F A2 01       LDX #$01                A:01FE X:0000 Y:0000 D:0000 DB:00 S:01FE P:envmXdIZC HC:0374 VC:000 FC:00 000
$00:8011 A9 00 42    LDA #$4200              A:01FE X:0001 Y:0000 D:0000 DB:00 S:01FE P:envmXdIzC HC:0390 VC:000 FC:00 000
$00:8014 5B          TCD                     A:4200 X:0001 Y:0000 D:0000 DB:00 S:01FE P:envmXdIzC HC:0414 VC:000 FC:00 000

funnyguy
Snes9x White Belt
Posts: 4
Joined: Sun May 01, 2016 12:16 pm

Re: CPU Cycle count relating to crystal clock count questio

Post by funnyguy » Wed Jul 26, 2017 8:05 am

Thanks OV2 for pointing that out. However where can I get the source code of the latest debug version ?
I can only found the prebuild version of Snes9X1.51.ep10r2.exe ( debug version ) and do not have source code to rebuild one myself.
Thanks

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