MVN and MVP instruction at bank boundary
Posted: Wed May 11, 2016 6:27 am
I check some document about the 65C816 processor,
they classify the MVN and MVP instructions are "new" instructions and therefore should cross boundaries.
So I wrote a short assembly code to test ( Opcode of MVP is 44, and I put it in 7EFFFF, the operands are in expected to be 7F0000, 7F0001 )
The memory content are
7E0000 : 55 55 55 55
....
7EFFFF : 44
7F0000 : 34 56
I trace it using SNES9X.
SNES9X fetches the operand from 7E0000 and 7E0001 instead of 7F0000 and 7F0001
and it wrapped in the bank $7E
after execution of this instruction, the next opcode fetched is 7E0002 ( not the 7F0002 )
Is that the actual performance a real 65C816 chip ?
they classify the MVN and MVP instructions are "new" instructions and therefore should cross boundaries.
So I wrote a short assembly code to test ( Opcode of MVP is 44, and I put it in 7EFFFF, the operands are in expected to be 7F0000, 7F0001 )
The memory content are
7E0000 : 55 55 55 55
....
7EFFFF : 44
7F0000 : 34 56
I trace it using SNES9X.
SNES9X fetches the operand from 7E0000 and 7E0001 instead of 7F0000 and 7F0001
and it wrapped in the bank $7E
after execution of this instruction, the next opcode fetched is 7E0002 ( not the 7F0002 )
Is that the actual performance a real 65C816 chip ?